Pin diagram of 8085 and Functions of various Pins

Pin Diagram of 8085

The below Diagram shows the Pin details of 8085:

Functions of various Pins of 8085

A8-A15 Higher Order Address bus:

These are o/p tri-state (a state of high impedance) signals used as higher order 8 bits of 16 bit address.

These signals are unidirectional and are given from 8085 to select memory or I/O devices.

AD0-AD7 Multiplexed Address/Data bus:

These are I/O tri-state signals, having 2 sets of signals. They are address and data.

The lower 8 bit of 16 bit address is multiplexed/time shared with data bus.

Address latch Enable(ALE):

It is an output signal used to give information of AD0-AD7 contents.

It is a positive going pulse generated when a new operation is started by microprocessor.

When pulse goes high it indicates that AD0-AD7 lines are address.

When it is low it indicates that the contents are data.

IO/M(bar):

This is an output status signal used to give info of operation to be performed with memory or I/O devices.

When = 0, the microprocessor is performing memory related operation.

When = 1, the microprocessor is performing I/O device related operation.

This signal separates memory and I/O devices.

Status signals(S0 and S1):

These are output status signals used to give information of operation performed by microprocessor.

The S0 and S1 lines specify 4 different conditions of 8085 machine cycles.

Read:

This is an active low output control signal used to read data from memory or an I/O device.

Write:

This is an active low output signal used to write data to memory or an I/O device.

Ready:

This is an active high input control signal.

It is used by microprocessor to detect whether a peripheral has completed (or is Ready for) the data transfer or not.

The main function of this pin is to synchronize slower peripheral to faster microprocessor.

If ready pin is high the microprocessor will complete the operation and proceeds for the next operation.

If ready pin is low the microprocessor will wait until it goes high.

Trap:

This is an active high, level and edge triggered, non-maskable higher priority interrupt.

When TRAP is active, the program counter of µp jumps automatically at address 0024.

RST 7.5,RST 6.5 and RST 5.5:

These are active high, edge (RST 7.5) or level (RST 6.5 and RST 5.5) triggered maskable interrupts.

The priorities of these are TRAP, RST 7.5, RST 6.5, and RST 5.5.

When RST 7.5, RST 6.5 and RST 5.5 are active, the program counter jumps automatically at address 003C, 0034, 002C respectively.

INTR and INTA(Bar):

INTR is an active high, level triggered general purpose interrupt.

When INTR is active µp generates an interrupt acknowledge signal.

If INTR is active, the Program Counter (PC) will be restricted from incrementing and an will be issued.

During This cycle a RESTART or CALL instruction can be inserted to jump to the interrupt Service routine.

The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.

HOLD:

HOLD indicates that another Master is requesting the use of the Address and Data Buses.

The CPU, upon receiving the Hold request, will withdraw the use of buses as soon as the completion of the current machine cycle. Internal processing can continue.

The processor can regain the buses only after the Hold is removed.

When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are tri-stated.

HLDA:

HOLD ACKNOWLEDGE indicates that the CPU has received the Hold request and that it will withdraw the buses in the next clock cycle.

HLDA goes low after the Hold Request is removed.

The CPU takes the buses one half clock cycles after HLDA goes Low.

ResetIN(Bar):

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA Flip-flops and makes address, data and control lines tri-stated.

The CPU is held in the reset condition as long as Reset is applied.

After reset status internal register and flag are unpredictable.

After reset microprocessor starts executing from instruction from 0000H onwards.

RESET OUT:

This is an active high output signal used to indicate CPU is being reset and can be used as a system RESET.

The signal is synchronized to the processor clock.

This signal is also used to reset the peripherals once the µP is reset.

It is an acknowledgement signal to RESET IN (bar).

Serial input data(SID):

This is an active high Serial input data line the data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.

Serial output data(SOD):

This is an active high Serial output data line.

The output SOD is set or reset as specified by the SIM instruction.

X1,X2:

Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal.

The input frequency is divided by 2 to give the internal operating frequency as shown in fig.

CLK OUT:

Clock Output for use as a system clock when a crystal or R/ C network is used as an Input to the CPU.

Clock input to all other peripherals is provided through CLK OUT pin.

The period of CLK is twice the X1, X2 input period.

VCC and VSS:

+5 volt supply and Ground Reference.